Tuesday 23 September
| 8:00 - 17:00 |
Tutorial: Compact Modelling, Theory and Practice |
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Wednesday 24 September
| 8:00 - 9:30 |
Registration |
9:30 - 9:40 |
Welcome address |
9:40 - 10:20 |
Invited talk 1: ON CHIP SOLID STATE COOLING FOR INTEGRATED CIRCUITS |
10:20 - 11:20 |
Session 1: ADVANCES IN SYSTEM LEVEL APPROACHES |
11:20 |
Break |
11:40 - 13:00 |
Vendors' session |
13:00 |
Lunch |
14:30 - 16.10 |
Session 2: RELIABILITY ISSUES AT PACKAGE AND SYSTEM LEVEL |
16.10 |
Break |
16.30 - 17.50 |
Session 3: THERMAL MODELLING AND CHARACTERISATION OF COMPONENTS |
17.50 |
Break |
18.10 - 19:00 |
Poster introduction and viewing session |
19:00 |
Cocktail |
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Thursday 25 September
| 8:30 - 9:10 |
Invited talk 2: CHIP- AND PACKAGE-LEVEL THERMAL MANAGEMENT OF POWER MODULES FOR FIELD RELIABILITY OF POWER SYSTEMS |
9:10 - 10:30 |
Session 4: DYNAMIC ANALYSIS OF ELECTRONIC PARTS AND SYSTEMS |
10:30 |
Break |
10.50 - 12.20 |
Panel |
12.20 |
Lunch |
13.50 - 15.10 |
Session 5: ELECTRO-THERMAL SIMULATION |
15.10 |
Break |
15.30 - 16:50 |
Session 6: MEASUREMENT METHODS |
19.00 |
Social event: Banquet |
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Friday 26 September
| 9.00 - 9.40 |
Embedded tutorial on JEDEC ACTIVITIES |
9.40 - 10.10 |
FINAL REPORT ON THE EC-FUNDED THERMAL PROJECT PROFIT |
10.10 |
Break |
10:30 - 12:00 |
Session 7: CALCULATION OF TEMPERATURE FIELDS |
12:00 |
Lunch |
13:30 - 14:50 |
Session 8: MEMS & THERMALLY OPERATED STRUCTURES |
14:50 |
Closing remarks |
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